LVDS on i.MX6

The i.MX6 series application processors from Freescale are a good choice for industrial and automotive applications requiring high multimedia performance. With the support of up to four simultaneously usable display ports the i.MX6 is also suitable for multi-display solutions or applications for high display resolutions.

Besides the conventional parallel 24-Bit RGB interface, there are also one HDMI, one MIPI DSI and two LVDS interfaces available. In this article we focus on the LVDS interfaces of the dual- and quad-core variants of the i.MX6 and explain the possible display configurations.


In the dual- and quad-core configuration, the i.MX6 comes with two Image Processing Units (IPU). Each IPU has two display ports which can be configured to send the image data either to the parallel RGB port or to the serializer bridges (HDMI, MIPI or LVDS).

The LVDS Display Bridge (LDB) is used to connect the IPU to external LVDS displays. With the two available LVDS channels the following configurations are supported:

  • Single Mode: only one LVDS channel is used (LVDS0 or LVDS1)
  • Dual Mode: one image stream is duplicated to both channels (LVDS0 = LVDS1)
  • Separate Mode: LVDS0 and LVDS1 are used to output different image streams. That’s the default setting to support multiple displays with different contents.
  • Split Mode: one image stream is split to both LVDS channels to get a high bandwidth for high resolution displays.


There are basically two limitations which have to be pointed out.

IPU capabilities

The two display ports (DI0 and DI1) of each IPU are limited to a combined pixel clock of 240MHz. The maximum clock for a single display port is 220MHz. This results in the following table (for one IPU only):

The table above only describes the capabilities of the display ports to perform screen refresh. A full use case typically includes additional activities like video processing, resizing etc., decreasing the possible display resolutions.

LVDS Serialization

Another limitation by using the LVDS interfaces is the maximum clock of the LVDS serializer. For single-channel output the pixel clock is limited to 85 MHz per LVDS port. This results in a maximum resolution of WXGA (1366x768 @ 60HZ with 35% blanking), for example. If a higher resolution is needed, the split mode has to be used. In this case one LVDS port outputs ODD data and the other port EVEN data. The pixel clock is limited to 170 MHz (e.g. UXGA 1600x1200 @ 60 Hz with 35% blanking). To use the split mode, you need a display supporting the dual channel LVDS mode in order to receive odd and even pixel data!


Before using the i.MX6 in applications with multiple displays or high resolution displays in your project, the limitations of the processor have to be carefully taken into account. emtrion supports you all the way to a successful project!